cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor
Visitor
223 Views
Registered: ‎03-23-2020

Constraints and bitstream generation

Jump to solution

I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board and familiar with Verilog modules/test bench as beginner. 

I have created a top module with an output 8-bit bus and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button).

Inside my top module I've three modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000.

Here is my constraint file:

 

# Clock Source - Bank 13
set_property PACKAGE_PIN Y9 [get_ports {CLK}]; # "GCLK"
# ----------------------------------------------------------------------------
# User LEDs - Bank 33
set_property PACKAGE_PIN T22 [get_ports {OUTPUT[0]}]; # "LD0"
set_property PACKAGE_PIN T21 [get_ports {OUTPUT[1]}]; # "LD1"
set_property PACKAGE_PIN U22 [get_ports {OUTPUT[2]}]; # "LD2"
set_property PACKAGE_PIN U21 [get_ports {OUTPUT[3]}]; # "LD3"
set_property PACKAGE_PIN V22 [get_ports {OUTPUT[4]}]; # "LD4"
set_property PACKAGE_PIN W22 [get_ports {OUTPUT[5]}]; # "LD5"
set_property PACKAGE_PIN U19 [get_ports {OUTPUT[6]}]; # "LD6"
set_property PACKAGE_PIN U14 [get_ports {OUTPUT[7]}]; # "LD7"
# User Push Buttons - Bank 34
# ---------------------------------------------------------------------------- 
set_property PACKAGE_PIN P16 [get_ports {RESET}]; # "BTNC"
set_property PACKAGE_PIN R16 [get_ports {stpGo}]; # "BTND"
# ----------------------------------------------------------------------------
# User DIP Switches - Bank 35
# --------------------------------------------------------------------------- 
set_property PACKAGE_PIN F22 [get_ports {ENA}]; # "SW0"
#set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
# ---------------------------------------------------------------------------
# IOSTANDARD Constraints
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. 
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
# Set the bank voltage for IO Bank 34 to 1.8V by default.
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
# Set the bank voltage for IO Bank 35 to 1.8V by default.
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. 
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets stpGo_IBUF];

 

I was able to simulate, synthesize, implement and generate Bitstream successfully. After all, then I tried to program my device and it came up with an error that I have no idea how to resolve the issue. 

zedboard error Image.jpeg

 

My constraint file is looking at my top-module ports only. I thought my other modules are internally connected and don't have to create a constraint file for each of them.

Please help me to understand and solve the issue.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Visitor
Visitor
58 Views
Registered: ‎03-23-2020

Re: Constraints and bitstream generation

Jump to solution

Thanks for the reply.

I was able to find and solve the issue with help of someone else out of this forum since I was waiting for help here.

The issue was my part #. I had to select chip xc7z040clg484 rather than xc7z020clg484. That fixed my issue immediately.

Thanks again for your time

MsDh

View solution in original post

6 Replies
Highlighted
Moderator
Moderator
217 Views
Registered: ‎06-05-2013

Re: Constraints and bitstream generation

Jump to solution

Can you share the device part number which you have selected? From the error message it seems part is incorrect.

 
 

2121.PNG

 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
203 Views
Registered: ‎03-23-2020

Re: Constraints and bitstream generation

Jump to solution
Here is my part: xc7z020clg484-2
I also tried xc7z020clg484-1 and got the same issue.
I forgot to say I am using Vivado 2018.2
0 Kudos
Highlighted
Moderator
Moderator
193 Views
Registered: ‎06-05-2013

Re: Constraints and bitstream generation

Jump to solution
Can you try any of the reference design? There are few on Zedboard website

Try to set the following parameter as well in Vivado HW manager.
set_param xicom.use_bitstream_version_check false

-Harshit

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
164 Views
Registered: ‎03-23-2020

Re: Constraints and bitstream generation

Jump to solution

Thanks for responds.

I couldn't try any reference design with the given link (I don't know which design should I try).

I restarted the Vivado and ran synthesize and implementation in order to generate Bitstream. Before all these steps I used your command to set Bitstream version check to "False" in my Tcl consul. After Bitstream generation was completed successfully I went to program my device but no Bitstream file was showing in dialog box to open. I browsed and selected a file in my impl_1 folder called CountingLED.bit. I had the same error messages after I ran "Program".

Please refer to the screenshots and let me know if I am not clear enough.

no bitstream file.jpeg

 

with bitstream file.jpeg

 

0 Kudos
Highlighted
Moderator
Moderator
96 Views
Registered: ‎06-05-2013

Re: Constraints and bitstream generation

Jump to solution
You can use any of the reference design bitstream just to make sure it is not a design issue.
If that is not possible please attach your design .bit file I can program my zedboard and share the results.

Thanks
Harshit
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Highlighted
Visitor
Visitor
59 Views
Registered: ‎03-23-2020

Re: Constraints and bitstream generation

Jump to solution

Thanks for the reply.

I was able to find and solve the issue with help of someone else out of this forum since I was waiting for help here.

The issue was my part #. I had to select chip xc7z040clg484 rather than xc7z020clg484. That fixed my issue immediately.

Thanks again for your time

MsDh

View solution in original post